1 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation sp6128a optimized for single supply, 3v - 5.5v applications high efficiency: greater than 95% possible discontinuous startup for precharged output accurate fixed 300khz frequency operation fast transient response internal soft start circuit accurate 0.8v reference allows low output voltages resistor programmable output voltage resistor programmable overcurrent threshold loss-less current limit with high side r ds(on) sensing hiccup mode current limit protection dual n-channel mosfet synchronous driver quiescent current: 500 a, 30 a in shutdown 14 pin tssop low v oltage, synchr onous step down pwm contr oller ideal for 2a to 10a, small footprint, dc-dc power converters applications dsp microprocessor core i/o & logic industrial control distributed power low voltage power the sp6128a is a fixed frequency, voltage mode, synchronous pwm controller designed to work from a single 5v or 3.3v input supply, providing excellent ac and dc regulation for high efficiency power conversion. requiring only few external components, the sp6128a pack- aged in an 14-pin tssop, is especially suited for low voltage applications where cost, small size and high efficiency are critical. the operating frequency is internally set to 300khz, allowing small inductor values and minimizing pc board space. the sp6128a drives two n-channel power mosfets for improved efficiency and includes an accurate 0.8v reference for low output voltage applications. 1 2 3 4 5 6 7 gl pv cc v cc pgnd gnd comp nc 14 13 12 1 1 10 9 8 bst gh swn i set v fb nc nc sp6128a 14 pin tssop bst swn v cc v fb comp gh gl gnd c1 2.2 f sp6128a q1 fds6690a c4 1 f d2 stps2l25u p v cc pgnd nc i set nc nc r1 5 1 2 3 4 5 6 7 14 13 12 11 10 9 8 c3 68pf r2 7.87k c2 4.7n r3 8k d1 mbr0530 l1 1.0 h q2 fds6690a c12 4.7nf r4 1.7k r5 800 c8 10 f c9 10 f c10 10 f c11 470 f 2.5v/10a c5 10 f c6 10 f c7 10 f 3v to 5.5v typical application circuit now available in lead free packaging description
2 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation parameter min typ max units conditions quiescent current v cc supply current 0.5 1.0 ma no switching pv cc supply current 1 20 a no switching, gh = low v cc supply current(disabled) 30 60 a comp=0v pv cc supply current (disabled) 1 20 a comp=0v error amplifier error amplifier transconductance 0.6 ms comp sink current 10 35 65 a v fb = 0.9v, comp = 0.9v, no faults comp source current 10 35 65 a v fb = 0.7v, comp = 2v comp output impedance 3 m ? v fb input bias current 130 na error amplifier reference 0.788 0.8 0.812 v trimmed with error amp in unity gain oscillator & delay path internal oscillator frequency 270 300 330 khz maximum controlled duty cycle 90 % loop in control - 100% dc possible minimum duty cycle 0 % comp=0.7v minimum gh pulse width 150 250 ns pv cc > 4.5v, ramp up comp voltage until gh starts switching current limit i set pin sink current 10 12.5 15 a temp = 25 c i set current temperature coefficient 3400 ppm/ c current limit time constant 15 s overcurrent comparator 100 125 150 mv vi set - v swn , temp = 25 c threshold voltage threshold voltage temperature 3400 ppm/ c coefficient electrical characteristics unless otherwise specified: -40 c < t a < 85 c, 3.0v < pv cc = v cc < 5.5v, c comp = 22nf, cgh = cgl = 3.3nf, v fb = 0.8v, swn = gnd = 0v, typical value for design guideline only. v cc, pv cc ......................................................................................... 7v bst .................................................................. 13.2v bst-swn .............................................................. 7v swn ............................................................ -1v to 7v gh ............................................... -0.3v to bst +0.3v gh-swn ............................................................... 7v all other pins ................................ -0.3v to v cc + 0.3v peak output current < 10 s gh,gl .................................................................. 2a storage temperature ........................ -65 c to 150 c power dissipation .............................................. 1.3w junction temperature, t j ................................ 125 c lead temperature (soldering, 10 sec) ............ 300 c esd rating. ................................................ 2kv hbm thermal resistance jc ............................. 31.7 c/w these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. absolute maximum ratings
3 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation pin description pin n0. pin name description 1 gl high current driver output for the low side mosfet switch. it is always low if gh is high. gl swings from pgnd to pv cc . 2 pv cc positive input supply for the low side gate driver. it's recommended to tie the pv cc to the v cc pin. 3 v cc positive input supply for the logic circuitry. properly bypass this pin to gnd with a low esl/ esr ceramic capacitor or rc filter. 4 pgnd power ground pin. 5 gnd signal ground pin. 6 comp output of the error amplifier. it is internally connected to the inverting input of the pwm comparator. a lead-lag network is typically connected to the comp pin to compensate the feedback loop in order to optimize the dynamic performance of the voltage mode control loop. sleep mode can be invoked by pulling the comp pin below 0.3v with an external open-drain or open-collector transistor. an internal 5 a pull-up ensures start-up. 7, 8, 9 nc no connect. 10 v fb feedback voltage pin. it is the inverting input of the error amplifier and serves as the output voltage feedback point for the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. 11 i set overcurrent program pin. a resistor programs the overcurrent threshold. the overcurrent comparator sets the fault latch and terminates gate pulses when vi set > v swn and the high side mosfet is turned on. this prevents excessive power dissipation in the external power mosfets during an overload condition. an internal delay circuit prevents false shutdowns that might otherwise occur during very short, mild overload conditions,due to load transients. 12 swn lower supply rail for the gh high-side gate driver. it also connects to the current limit comparator. connect this pin to the switching node at the junction between the two external power mosfet transistors. this pin monitors the voltage drop across the r ds(on) of the high side n-channel mosfet while it is conducting. 13 gh high current driver output for the high side mosfet switch. it is always low if gl is high or during a fault. gh swings from swn to bst. 14 bst high side driver supply pin. connect bst to the external boost diode and capacitor as shown in the application schematic on page 1. electrical characteristics unless otherwise specified: -40 c < t a < 85 c, 3.0v < pv cc = v cc < 5.5v, c comp = 22nf, cgh = cgl = 3.3nf, v fb = 0.8v, swn = gnd = 0v, typical value for design guideline only. parameter min typ max units conditions soft start, shutdown, uvlo internal soft start slew rate 0.1 0.3 0.6 v/ms comp pin, on transition from shutdown comp discharge current 183 a comp = 0.5v, fault initiated comp clamp voltage 0.55 0.65 0.75 v v fb = 0.9v comp clamp current 10 30 65 a comp = 0.5v, v fb = 0.9v shutdown threshold voltage 0.29 0.34 0.39 v measured at comp pin shutdown input pull-up current 2 5 10 a comp = 0.2v, measured at comp pin v cc start threshold 2.63 2.8 2.95 v v cc stop threshold 2.47 2.7 2.9 v gate drivers gh rise time 60 110 ns pv cc > 4.5v gh fall time 60 110 ns pv cc > 4.5v gl rise time 60 110 ns pv cc > 4.5v gl fall time 60 110 ns pv cc > 4.5v gh to gl non-overlap time 0 100 140 ns pv cc > 4.5v, measured at 2volt threshold gl to gh non-overlap time 0 100 140 ns pv cc > 4.5v, measured at 2volt threshold
4 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation general overview the sp6128a is a constant frequency, voltage mode, synchronous pwm controller designed for low voltage, dc/dc step down converters. it is intended to provide complete control for a high power, high efficiency, precisely regulated output voltage from a highly integrated 14-pin solution. the internal free-running oscillator accurately sets the pwm frequency at 300khz without requiring any external elements and allows the use of physically small, low value external com- ponents without compromising performance. a transconductance amplifier is used for the error amplifier, which compares an attenuated sample of the output voltage with a precision, 0.8v reference voltage. the output of the error ampli- fier (comp), is compared to a 0.75v peak-to- peak ramp waveform to provide pwm control. the comp pin provides access to the output of the error amplifier and allows the use of external components to stabilize the voltage loop. high efficiency is obtained through the use of synchronous rectification. synchronous regula- tors replace the catch diode in the standard buck con v e r t e r w i t h a l o w r d s ( o n ) n - c h a n n e l mosfet switch allowing for significant ef- f i c i e n c y i m p r o v e m e n t s . t h e s p 6 1 2 8 a i n - cludes two fast mosfet drivers with inter- nal non-overlap circuitry and drives a pair of n-channel power transistors. the sp6128a includes an internal 0.27v/ms soft-start cir- cuit that provides controlled ramp up of the output voltage, preventing overshoot and in- rush current at power up. current limiting is implemented by monitoring the voltage drop across the r ds(on) of the high side n-channel mosfet while it is conducting, thereby eliminating the need for an external sense resistor. the overcurrent threshold can be programmed by a single resistor. functional diagram + - - + - + synchronous driver pwm logic s q r reset dominant r q s v cc swn reference 6 10 0.8v uvlo f aul t swn 12 1 gl 13 driver enable reset dominant pwm comp f aul t gh gh 5 a 350mv shutdown gm error amp over current 2.8v on 2.7v off comp shutdown f = 300khz 750mv ramp 0.27v/ms softst art v fb comp 3 - + - + 1v + - gnd 5 14 bst i set 15 a 2 pv cc 1 1 pgnd 4 operation
5 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation when the overcurrent threshold is exceeded, the overcurrent comparator sets the fault latch and terminates the output pulses. the controller stops switching and goes through a hiccup se- quence. this prevents excessive power dissipa- tion in the external power mosfets during an overload condition. an internal delay circuit prevents that very short and mild overload con- ditions, that could occur during a load transient, activate the current limit circuit. a low power sleep mode can be invoked in the sp6128a by externally forcing the comp pin below 0.3v. quiescent supply current in sleep mode is typically less than 30 a. an internal 5 a pull-up current at the comp pin brings the sp6128a out of shutdown mode. an internal 0.8v 1.5% reference allows out- put voltage adjustment for low voltage appli- cations. the sp6128a also includes an accurate under- voltage lockout that shuts down the controller when the input voltage falls below 2.7v. output overvoltage protection is achieved by turning off the high side switch and turning on the low side n-channel mosfet 100% of the time. enable low quiescent mode or ?leep mode?is initi- ated by pulling the comp pin below 0.3v with an external open-drain or open-collector tran- sistor. supply current is reduced to 30 a (typi- cal) in shutdown. on power-up, assuming that v cc has exceeded the uvlo start threshold (2.8v), an internal 5 a pull-up current at the comp pin brings the sp6128a out of shutdown mode and ensures start-up. during normal oper- ating conditions and in absence of a fault, an internal clamp prevents the comp pin from swinging below 0.6v. this guarantees that dur- ing mild transient conditions, due either to line or load variations, the sp6128a does not enter shutdown unless it is externally activated. during sleep mode, the high side and low side mosfets are turned off and the internal soft start voltage is held low. uvlo assuming that there is not shutdown condition present, then the voltage on the v cc pin deter- mines operation of the sp6128a. as v cc rises, the uvlo block monitors v cc and keeps the high side and low side mosfets off and the internal ss voltage low until v cc reaches 2.8v. if no faults are present, the sp6128a will ini- tiate a soft start when v cc exceeds 2.8 v. hysteresis (about 100mv) in the uvlo com- parator provides noise immunity at start-up. soft start soft start is required on step-down controllers to prevent excess inrush current through the power train during start-up. typically this is managed by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up either the error amp reference or the error amp output (comp). the control loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady-state duty cycle as the output voltage increases to its regu- lated value. as a result of controlling the induc- tor volt*second product during startup, inrush current is also controlled. in the sp6128a the duration of the soft-start is controlled by an internal timing circuit that provides a 0.3v/ms slew-rate, which is used during startup and overcurrent to set the hiccup time. the sp6128a implements soft-start by ramping up the error amplifier reference voltage providing a controlled slew-rate of the output voltage, thereby preventing overshoot and in- rush current at power up. the presence of the output capacitor creates extra current draw during startup. simply stated, dv out / dt requires an average sustained current in the output capacitor and this current must be consid- ered while calculating peak inrush current and over current thresholds. an approximate expres- sion to determine the excess inrush current due to the dv out /dt of the output capacitor c out is: iinrush = c out x (0.27 v/ms) x v out 0.8v operation: continued
6 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation as the figure shows, the ss voltage controls a variety of signals. first, provided all the exter- nal fault conditions are removed, an internal 5 a pull-up at the comp pin brings the sp6128a out of shutdown mode. the internal timing circuit is then activated and controls the ramp-up of the error amp reference voltage. the comp pin is pulled to 0.7v by the internal clamp and then gradually charges preventing the error amplifier from forcing the loop to maximum duty cycle. as the comp voltage crosses about 1v (valley voltage of the pwm ramp), the driver begins to switch the high side mosfet with narrow pulses in an effort to keep the converter output regulated . the sp6128a operates at low duty cycle as the comp voltage increases above 1v. as the error amp reference ramps upward, the driver pulses widen until a steady state value is reached and the output voltage is regulated to the final value ending the soft start charge cycle. hiccup mode when the converter enters a fault mode, the sp6128a holds the high side and low side mosfets off for a finite period of time. provided that the sp6128a is enabled, this time is set by the internal charge of the soft-start capacitor. in the event of an overcurrent condition, the current sense comparator sets the fault latch, which in turn discharge the internal ss capacitor, the comp pin and holds the output drivers off. during this con- dition, the sp6128a stays off for the time it takes to discharge the comp pin down to the 0.29v shutdown threshold. at this point, the fault latch is reset, but before the sp6128a is allowed to attempt restart, the comp pin has to charge back to 1v before any output switching can be initiated. then, the regulator attempts to restart normally by delivering short gate pulses and if the overcurrent condition is still present, the cycle will repeat itself. however, if upon restart, the overcurrent condi- tion is still present, the sp6128a will detect the fault and remain in a fault state until the internal soft start voltage reaches about v cc -1v thereby increasing the mosfet off-time. this protection scheme minimizes thermal stress to the regulator components as the overcurrent condition persists. operation: continued 0.8 v i(l) time 0.3 v 0.7 v 1 v 0 v comp internal ss 0 v swn v oltage v oltage f a ul t current inductor 0 a v oltage reference err or amp 0 v v(v cc ) 0 v v(v cc )
7 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation sp6128a over current (hiccup mode) test conditions v fb = 0.7v v cc = pv cc = 5.0v a more detailed description of the waveform is shown below. over current protection over current protection on the sp6128a is imple- mented through detection of an excess voltage condition across the high side nmos switch during conduction. this is typically referred to as high side r ds(on) detection and eliminates the need of an external sense resistor. the over current comparator charges an internal sam- pling capacitor each time v swn is lower than (v iset - 140mv) and the gh voltage is high. the discharge/charge current ratio on the sampling capacitor is about 2%. therefore, provided that the over current condition persists, the capacitor voltage will be pumped up during each time gh switches high. this voltage will trigger an over current condition upon reaching a cmos in- verter threshold. there are many advantages to this approach. first, the filtering action of the gated scheme protects against false and undesir- able triggering that could occur during a minor transient overload condition or supply line noise. furthermore, the total amount of time to trigger the fault depends on the on-time of the high side nmos switch. fifteen, 1 s pulses are equiva- lent to thirty, 500ns pulses or one, 15 s pulse, however, depending on the period, each sce- nario takes a different amount of total time to trigger a fault. therefore, the fault becomes an indicator of average power in the high side bst = 5.0v swn - tied to gnd through 1k resistor comp ?released from gnd internal sst art passes v(v fb ), comp pops t o ~ internal sst art vol t age +0.7v internal sst art rises until ~ v cc -1v , then gives command to attempt rest art comp clamps ~ 3v after pop, comp retains internal sst art slope enable part a ttempt rest art 5 a pullup slope to 0.3v; 35 a pullup to 0.7v overcurrent detected g h t urns off fault mode enabled g h comp operation: continued
8 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation - v(diode) v ~ 0 v 5 v non-overlap gh(gl) 10 % 90 % f all time 2 v gl(gh) 10 % 90 % rise time 5 v 2 v ga te driver test conditions time ~ 2*v(vin) ~ v(vin) bst v oltage swn v(vcc=vin) v oltage v oltage v oltage v(bst) gl gh v(vcc) 0 v 0 v switch. the i set current has a temperature coef- ficient in an effort to first order match the thermal characteristics of the r ds(on) of the high side nmos switch. it assumed that the sp6128a will be used in compact designs where there is a high amount of thermal coupling between the high side switch and the controller. discontinuous start up today? distributed power systems require mul- tiple supply voltages, such as core and i/o voltages. in many applications, there? require- ment on the maximum voltage difference al- lowed between these supplies at any time. this requirement can be potentially violated during power start up when individual power supply ramps up in sequence or in different slew rates. as a solution, system designers often pre-charge power supplies through an external circuit prior to start up. unfortunately, under this condition many existing synchronous controllers turn on the low side mosfet during soft start for a long period of time, thereby, discharging the output capacitors. the discharge period creates a number of problems. one is the obvious prob- lem of losing the intended pre-charged output voltage. another problem is a build up of exces- sive and unchecked current in the low side mosfet and inductor. lastly, this uncontrolled discharge current creates conditions that could damage either the distributed power supplies or the rather expensive ?oad?ics. to prevent soft start from discharging the pre- charged output, sp6128a has built-in discon- tinuous start up. this operation disables the low side mosfet driver gl during start up until either there is gh pulse or the internal sstart reaches vcc-1v. this feature eliminates the output discharging path during start up. during the steady state operation, the gl is fully en- gaged, and the operation is identical to regular synchronous buck converters. output drivers the sp6128a, unlike some other bipolar con- troller ic?, incorporates gate drivers with rail- to-rail swing that help prevent spurious turn on due to capacitive coupling. the driver stage consists of one high side nmos, 4 ? driver, gh, and one low side, 4 ? , nmos driver, gl, optimized for driving external power mosfet? in a synchronous buck topology. the output drivers also provide gate drive non-overlap mechanism that provides a dead time between gh and gl transitions to avoid potential shoot- through problems in the external mosfets. the following figure shows typical waveforms for the output drivers. as with all synchronous designs, care must be taken to ensure that the mosfets are properly chosen for non-overlap time, enhancement gate drive voltage, ?n?resistance r ds(on) , reverse transfer capacitance crss, input voltage and maximum output current. operation: continued
9 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corporation gage plane 1.0 oia e 0.169 (4.30) 0.177 (4.50) 0.252 bsc (6.4 bsc) 0 -8 12?ef 0.039 (1.0) e/2 0.039 (1.0) 0.126 bsc (3.2 bsc) d 0.007 (0.19) 0.012 (0.30) 0.033 (0.85) 0.037 (0.95) 0.002 (0.05) 0.006 (0.15) 0.043 (1.10) max ( 3) 1.0 ref 0.020 (0.50) 0.026 (0.75) ( 1) 0.004 (0.09) min 0.004 (0.09) min 0.010 (0.25) ( 2) 0.008 (0.20) dimensions in inches (mm) minimum/maximum symbol 14 lead d 0.193/0.201 (4.90/5.10) e 0.026 bsc (0.65 bsc) plastic thin small outline (tssop) package: tssop
10 rev. 08/19/05 sp6128a low voltage, synchronous step down pwm controller ?copyright 2005 sipex corpor ation corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liabil ity arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent righ ts nor the rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 ordering information part number operating temperature range package type sp6128aey ............................................ -40?c to +85?c ...................................... 14-pin tss op sp6128aey/tr ...................................... -40?c to +85?c ...................................... 14-pin tssop sp6128ahy ........................................... -40?c to +105?c ..................................... 14-pin tssop sp6128ahy/tr ..................................... -40?c to +105?c ..................................... 14-pin tssop available in lead free packaging. to order add "-l" suffix to part number. example: sp6128aey/tr = standard; sp6128aey-l/tr = lead free /tr = tape and reel pack quantity is 2,500 for tssop. sp6128acy .............................................. 0?c to +70?c ....................................... 14-pin ts sop sp6128acy/tr ........................................ 0?c to +70?c ....................................... 14-pin tssop
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